WDC 65C21: Difference between revisions
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[[Image:W65C21S6TPG-14 lg.jpg|thumb|WDC W65C21S Peripheral Interface Adapter (PIA)]] | [[Image:W65C21S6TPG-14 lg.jpg|thumb|WDC W65C21S Peripheral Interface Adapter (PIA)]] | ||
The '''W65C21S''' is a Peripheral Interface Adapter (PIA) for use with WDC's 65xx and other 8-bit microprocessor families. It was produced by [[Western Design Center|Western Design Center (WDC)]]. | |||
== | The W65C21S provides programmed microprocessor control of up to two peripheral devices (Port A and Port B). Peripheral device control is accomplished through two 8-bit bidirectional [[I/O]] Ports, with individually designed Data Direction Registers. The Data Direction Registers provide selection of data flow direction (input or output) at each respective I/O Port. Data flow direction may be selected on a line-by-line basis with intermixed input and output lines within the same port. The "handshake" interrupt control feature is provided by four peripheral control lines. This capability provides enhanced control over data transfer functions between the microprocessor and peripheral devices, as well as bidirectional data transfer between W65C21S [[Peripheral Interface Adapter]]s in multiprocessor systems.<ref>{{Cite web|url=https://www.westerndesigncenter.com/wdc/documentation/w65c21.pdf|date=March 18, 2024|author=THE WESTERN DESIGN CENTER, INC.|title=W65C21 (W65C21N and W65C21S) Peripheral Interface Adapter (PIA)}}</ref> | ||
The PIA interfaces to the 65xx microprocessor family with a reset line, a Φ2 clock line, a read/write line, two interrupt request lines, two register select lines, three chip select lines and an 8-bit bidirectional data bus. The PIA interfaces to the peripheral devices with four interrupt/control lines and two 8-bit bidirectional buses. | |||
The | |||
The W65C21S | The W65C21S PIA is organized into two independent sections referred to as the A Side and the B Side. Each section consists of Control Register (CRA, CRB), Data Direction Register (DDRA, DDRB), Output Register (ORA, ORB), Interrupt Status Control (ISCA, ISCB) and the buffers necessary to drive the Peripheral Interface buses. Data Bus Buffers (DBB) interface data from the two sections to the data bus, while the Date Input Register (DIR) interfaces data from the DBB to the PIA registers. Chip Select and RWB control circuitry interface to the processor bus control lines. | ||
==References== | |||
{{reflist}} | |||
==External links== | |||
*[https://www.wdc65xx.com/wdc/documentation/w65c21s.pdf W65C21S Datasheet] | |||
[[Category:Input/output integrated circuits]] | |||
Latest revision as of 05:28, 29 September 2026
The W65C21S is a Peripheral Interface Adapter (PIA) for use with WDC's 65xx and other 8-bit microprocessor families. It was produced by Western Design Center (WDC).
The W65C21S provides programmed microprocessor control of up to two peripheral devices (Port A and Port B). Peripheral device control is accomplished through two 8-bit bidirectional I/O Ports, with individually designed Data Direction Registers. The Data Direction Registers provide selection of data flow direction (input or output) at each respective I/O Port. Data flow direction may be selected on a line-by-line basis with intermixed input and output lines within the same port. The "handshake" interrupt control feature is provided by four peripheral control lines. This capability provides enhanced control over data transfer functions between the microprocessor and peripheral devices, as well as bidirectional data transfer between W65C21S Peripheral Interface Adapters in multiprocessor systems.[1]
The PIA interfaces to the 65xx microprocessor family with a reset line, a Φ2 clock line, a read/write line, two interrupt request lines, two register select lines, three chip select lines and an 8-bit bidirectional data bus. The PIA interfaces to the peripheral devices with four interrupt/control lines and two 8-bit bidirectional buses.
The W65C21S PIA is organized into two independent sections referred to as the A Side and the B Side. Each section consists of Control Register (CRA, CRB), Data Direction Register (DDRA, DDRB), Output Register (ORA, ORB), Interrupt Status Control (ISCA, ISCB) and the buffers necessary to drive the Peripheral Interface buses. Data Bus Buffers (DBB) interface data from the two sections to the data bus, while the Date Input Register (DIR) interfaces data from the DBB to the PIA registers. Chip Select and RWB control circuitry interface to the processor bus control lines.
References
- ↑ THE WESTERN DESIGN CENTER, INC. (March 18, 2024). "W65C21 (W65C21N and W65C21S) Peripheral Interface Adapter (PIA)". https://www.westerndesigncenter.com/wdc/documentation/w65c21.pdf.